1. Field of the Invention
The present invention relates to a method for producing deep trench structures in an STI structure of a semiconductor substrate.
2. Description of the Background Art
The increasing integration of highly integrated and very highly integrated semiconductor components is taking on ever greater importance in the development of these semiconductor components. Not least for this reason, the semiconductor components or individual semiconductor structures are increasingly being moved deeper into the semiconductor substrate. This practice requires trenches, for example for lateral insulation of the components.
A method for producing trenches is called the deep trench method (DT=deep trench), in which deep trenches are etched in the semiconductor substrate and preferably filled with a combination of insulating materials and/or polysilicon. Deep trench structures are used in order to electrically insulate semiconductor components from one another that are constructed in adjacent cells of a cell structure. Furthermore, provision can also be made for an insulated electrode to be introduced into a deep trench structure so that the deep trench structure is designed as an electrode, for example as an electrode of a capacitor for a trench capacitor of a semiconductor memory. The depth of these trenches not only minimizes parasitic capacitances between semiconductor components, but also reduces substrate-related interference. Modern deep trench structures achieve aspect ratios of 40 and above; the aspect ratio designates the ratio of a trench's depth to its width.
In addition or as an alternative to these deep trench structures, modern semiconductor components also use shallow trench structures (STI). STI structures are used for such purposes as electrically separating buried conductive traces or substructures of semiconductor components from one another in highly complex semiconductor components. Shallow trench insulation is also used to increase the integration density (known as the packaging density) and to reduce specific component capacitances.
With modern semiconductor components, there is a need to integrate logic elements, which are designed for a relatively low supply voltage, along with power semiconductor components, which are exposed to voltages that are much higher in comparison thereto, together in one semiconductor chip. For this implementation, it is advantageous for the deep trench technology to be combined with the shallow trench technology. In these applications, the deep trench structures are integrated in the areas of the shallow trench structures, so that no additional space requirement results from the use of the two technologies.
A method for creating combined STI structures and deep trench structures is described below with reference to FIG. 2A-FIG. 2E.
FIG. 2A shows a semiconductor substrate 1, which contains two STI regions 2a, 2b, and an active region 3 located between them. In the STI regions 2a, 2b, areas that are intended for an STI structure have been etched out of the surface 4 of the semiconductor substrate 1. The active region 3 has a layer stack 5 for defining a hard mask. A full-area hard mask layer 6 was applied to both the STI region 2a, 2b and the active region 3, and a lacquer mask layer 7 was applied to said hard mask layer 6 (FIG. 2B). The lacquer mask 7 is then appropriately structured in the area of the STI region 2b, and the hard mask 6 is then structured using the lacquer mask 7 (FIG. 2B). The lacquer mask 7 is then removed. Using the window 8a on the hard mask 6, a deep trench 8 is etched in the area of the STI region 2b (FIG. 2C) and is then filled with oxide or polysilicon. This filler material 9 that has been deposited on the surface of the hard mask 6 is then etched back. The removal of the hard mask 6 (FIG. 2D) then follows. Finally, in order to produce the individual STI structures in the area of the STI regions 2a, 2b, the recesses there are filled with an STI filler material 10, for example silicon dioxide (FIG. 2E). This is followed by leveling of the surface of the semiconductor structure, and thus at least partial removal of the layer stack 5, for example by a CMP process.
An idealized method for producing combined STI and deep trench structures has been described using FIGS. 2A-2E. However, the method described there results in several problems that will be discussed briefly below.
During application of the layer stack 5, a step 11 is produced between the active region 3 and the adjacent STI regions 2a, 2b. During the subsequent application of the hard mask 6 and the lacquer mask 7, this step 12 remains in the topography of the lacquer mask 7, with the net result that the surface of the lacquer mask 7 is not flat, but rather has a wavy shape. This is referred to as a vertical, wavy topography of the lacquer mask 7. This wavy topography also results in a varying thickness D3 of the lacquer layer 7, which is to say that D3≠constant. In the semiconductor process, the lacquer mask 7 serves to structure the hard mask 7, which in turn serves to structure the deep trench structures 8. It is problematic here that a vertical topography of the lacquer mask 7 and the hard mask 6 does not permit exact structuring of the semiconductor component and thus exact structuring of the trenches 8 that are to be produced.
The primary problem here is to expose all areas of the lacquer layer 7 homogeneously, which is to say with the same exposure dose, in order to be able to uniformly open the corresponding structures in the lacquer layer 7. However, a differing lacquer layer thickness D3 has the result that different exposure doses are required for the different lacquer layer thicknesses D3. Since this cannot be achieved in practice in the semiconductor process, all areas of the lacquer layer are typically exposed with the maximum exposure dose corresponding to the maximum lacquer layer thickness D3; however, this has the direct result that openings of different widths are produced in the lacquer mask 7. This results in different CD dimensions (CD=critical dimension) for the structures to be exposed. On the whole, this means that, as a result, the process for structuring the lacquer mask 7 and hence for producing the hard mask 6 cannot be precisely controlled, so that trenches 8 of different widths are produced. This is undesirable, particularly when the structures to be produced have very small structure widths for which the CD is relevant.
The vertical wavy topography also results in differing thicknesses D4 of the applied filler material 9 (e.g. polysilicon), which is to say that D4≠constant. This differing thickness D4 of the filler material 9 then continues into the area of the trenches 8. When etching back the filler material 9 from the trenches 8, cavities or voids can be formed in the trenches 8. Cavities or voids are typically unwanted hollow spaces that are formed in processing when the trenches are filled in. Overall, this results in an inhomogeneous filling of the trenches 8, so that the trenches 8 typically lack some or all of the properties (e.g., insulation) that are assigned to them. Inhomogeneous filling of the trenches 8 can also have the result that a different fill height of the filler material remaining in the trenches 8 is achieved when etching back the filler material 9 from the trenches 8. This is also undesirable, since this inhomogeneity of the filling of the trenches 8 must also be taken into account in further processing, with the result that the overall process flow is more complicated and/or that the trench-shaped structures produced thereby are qualitatively worse.
Another problem results when etching back the filler material from the trenches 8. During this back-etching, residue from the filler material can be deposited in the edge region between the STI region 2b and the active region 3. However, it can be very difficult to remove this deposited residue in a later process step. Moreover, during back-etching it is possible for so-called spacers to form; these are also undesirable during the further course of processing.